ISL6112INZA-T【PDF 16/30 页】IC PWR CNTRLR DUAL SLT 48-TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录38

12页 13页 14页 15页 [16页]17页 18页 19页 20页

ISL6112

FN6456.1

August 25, 2011

undervoltage condition on either of the MAIN supply inputs is

detected, INT

also asserts, if interrupts are enabled.

Enabling the MAIN GATE Outputs

When a slot's MAIN supplies are off, the 12VGATE pin is held high

with an internal pull-up to the 12VIN voltage. Similarly, the

3VGATE pin is internally held low to GND. When the MAIN

supplies of the ISL6112 are enabled by asserting ON, the related

3VGATE and 12VGATE pins are each connected to a constant

current supply. For the 3VGATE pin, this supply is nominally a

25礎 current source. For the 12VGATE pin, the supply is

nominally a -25礎 current sink. The 3VGATE is charged up to the

12VIN voltage, while the 12GATE is pulled down to GND, for

maximum enhancement of the N-Channel and P-Channel FETs,

respectively.

Estimating In-Rush Current and V

OUT

Slew

Rate at Start-Up

The expected in-rush current can be estimated by using

Equation1:

where 25礎 is the GATE pin charge current, and C

LOAD

is the

load capacitance. C

GATE

is the total GATE capacitance, including

ISS

of the external MOSFET and any external capacitance

connected from the GATE output pin to the GATE reference, GND,

or source.

An estimate for the output slew rate of 3.3V outputs and 12V

outputs, where there is little or no external 12VGATE output

capacitors, can be determined from Equation 2:

where I

LIM

= 50mV/R

SENSE

and C

LOAD

is the load capacitance.

As a consequence, the CR duration, t

FILTER,

must be

programmed to exceed the time it takes to fully charge the

output load to the input rail voltage level.

MAIN Outputs (Start-up Delay and Slew-Rate

Control)

The 3.3V outputs act as source followers. In this mode of

operation, V

SOURCE

= [V

GATE

TH(ON)

] until the associated

output reaches 3.3V. The voltage on the gate of the MOSFET

continues to rise until it reaches 12V, which ensures minimum

DS(ON)

. For the 12V outputs, the MOSFET can be optionally

configured as a Miller integrator by adding a C

capacitor

connected between the MOSFET's gate and drain to adjust the

VOUT ramp time. In this configuration, the feedback action from

drain to gate of the MOSFET causes the voltage at the drain of

the MOSFET to slew in a linear fashion at a rate estimated by

Equation 3:

Table 1 approximates the output slew-rate for various values of

GATE

when start-up is dominated by GATE capacitance (external

GATE

from GATE pin to ground, plus C

of the external MOSFET

for the 3.3V rail and C

for the 12V rail).

Note that all of these performance estimates are useful only for

first-order time and loading expectations, because they do not

look at other significant loading factors. Figures 18, 19, 20, 21

and 22 illustrate empirically the discussed turn-on performance

with the noted loading and compensation conditions.

Notice the degree of control over the in-rush current and the

GATE ramp rate as the values are changed, which provides for

highly customizable turn-on characteristics.

In some scope shots, although the C

FILTER

shows ramping in the

absence of excessive displayed loading current, C

FILTER

responding to the other MAIN supply current that is not

displayed.

All scope shots were taken from the ISL6112EVAL1Z, with any

component changes noted.

Current Regulation (CR) Function

The ISL6112 provides a current regulation and limiting function

that protects the input voltage supplies against excessive loads,

including short circuits. When the current from any slots MAIN

outputs exceeds the current limit threshold (I

LIM

= 50mV/R

SENSE

)

for a duration greater than t

FILTER

, the isolation protection is

tripped, and both related MAIN supplies are shut off, as shown in

Figures 28 and 29. Should the load current cause a MAIN output

SENSE

to exceed V

THFAST

, the output is immediately shut off, with

no t

FILTER

delay, as shown in Figures 28 and 29.

The VAUX outputs have a different isolation protection function.

The VAUX isolation circuit does not incorporate a fast-trip

detector; instead, they regulate the output current into a fault to

avoid exceeding their operating current limit. The protection

circuit trips due to an overcurrent on VAUX when the

programmable CR duration timer, t

FILTER

, expires. This use of the

FILTER

timer prevents the circuit from tripping prematurely due

to brief current transients. See Figures 25 and 26 for illustrations

of the VAUX protection performance into a slight OC and more

severe OC condition, respectively. The ISL6112 AUX current

control responds proportionally to the severity of the OC

condition, resulting in faster VAUX pull-down and current

regulation until t

FILTER

has expired.

Following a fault condition, the outputs can be turned on again

(1) via the ON inputs if the fault occurred on one of the MAIN

outputs), (2) via the AUXEN inputs if the fault occurred on the AUX

outputs, or (3) by cycling both ON and AUXEN if faults occurred on

(EQ. 1)

IN RUSH

NOMINALLY 25糀

LOAD

GATE

-----------------

?nbsp ?/DIV>

(EQ. 2)

dv/dt VOUT NOMINALLY

LIM

LOAD

-----------------

(EQ. 3)

dv/dt VOUT NOMINALLY

25糀

---------------

TABLE 1. 3.3V AND 12V OUTPUT SLEW-RATE SELECTION FOR GATE

CAPACITANCE DOMINATED START-UP

| IGATE | = 25礎

CGATE or C

dv/dt (load)

0.01礔 (Note)

2.5V/ms

0.022礔 (Note)

1.136V/ms

0.047礔

0.532 V/ms

0.1礔

0.250V/ms

NOTE: Values in this range are affected by the internal parasitic

capacitances of the MOSFETs used, and should be verified

experimentally.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式